1. Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate for a liquid crystal display, and more particularly, to a TFT array substrate having a black matrix and its fabrication method
2. Discussion of the Related Art FIG. 1A is a plan view showing the structure of a TFT array substrate (lower substrate) for a conventional TFT liquid crystal display.
Pixels are arranged in a matrix on the lower substrate. Each pixel has a pixel electrode 17 connected to the TFT, a switching device, and a drain electrode 11D of the TFT. A gate bus line (gate bus) 13L formed in one direction is connected to a gate electrode 13G of the TFT formed at each pixel. A data bus line (data line) 11L formed in the direction crossing the gate bus line is connected to a source electrode 11S of the TFT.
On another substrate (upper substrate, not shown), there is provided a black matrix (light shielding layer) for shielding an opaque portion of the lower substrate and a portion which causes light leakage. In FIG. 1A, dotted lines 21 represent the black matrix pattern projected onto the lower substrate from the upper substrate.
FIGS. 1B and 1C are cross-sectional views of the upper and lower substrates of the liquid crystal display taken along lines I--I and II--II in FIG. 1A, respectively. These figures show the portion near the data bus line and the portion near the TFT, respectively.
Referring to FIG. 1C a gate electrode 13G made of a metal is formed on the lower substrate 10. An island-shaped active layer 15 of a semiconductor material is formed over the gate electrode 13G together with a gate insulating layer 12 over the substrate. An ohmic contact layer 14 of a doped semiconductor material is formed on the active layer 15. A source electrode 11S and a drain electrode 11D are formed on the ohmic contact layer 14. The source electrode 11S extends to a data bus line 11L formed on the gate insulating layer 12. A protective layer 16 is formed on the data bus line 11L, source electrode 11S, drain electrode 11D, the exposed portion of the active layer 15, and the exposed portion of the gate insulating layer 12. A pixel electrode 17 connected to the drain electrode 11D via a contact hole formed in the protective layer 16 is formed on the protective layer 16. The top layer above the pixel electrode 17 is an orientation layer 19.
On an upper substrate 20, a black matrix 21 is formed to shield the TFT, the data bus line 11, and the gate bus line 13L of the lower substrate 10. Here, the black matrix 21 is formed in consideration of the margin at the attachment area of the upper and lower substrates and for preventing light leakage at the margin. Besides the black matrix 21, a color filter 22, a common voltage electrode 23, and an orientation layer 24 are formed on the upper substrate 20, respectively.
In the conventional liquid crystal display, the black matrix is formed on the upper substrate. Thus, the margin for misalignment in the attachment of the upper and lower substrates must be considered. As a result, the size of the black matrix must be large, which makes the aperture ratio of the liquid crystal display to be small. In addition, because the black matrix is made of a metal such as chrome, a parasitic capacitance problem due to its conductivity and a light reflection problem due to its high reflection coefficient exist.
FIGS. 2A and 2B show an alternative technique in which the black matrix is formed on the lower substrate in order to solve the above problem concerning the aperture ratio. Here, the black matrix is made of an opaque insulating resin, thus solving the light reflection and the parasite capacitance problems caused by using a black matrix made of a metal.
As shown in FIG. 2B, the substrate has a gate electrode 13G, a gate insulating layer 12, and an active layer 15. The active layer 15 is formed on the gate insulating layer 12 so as to cover the gate electrode 13G. An ohmic contact layer 14 is formed on the active layer 15. A pixel electrode 17 is formed to be spaced from the ohmic contact layer 14 and the active layer 15 by predetermined distances. A source electrode 11S and a drain electrode 11D are formed to be in contact with the ohmic contact layer 14. Here, the source electrode 11S is connected to the data bus line 11, as shown in FIG. 2B. The drain electrode 11D is connected to the pixel electrode 17. A protective layer 16 is formed under the pixel electrode 17 and over the source electrode 11S and the drain electrode 1D. A black matrix 18 of an opaque insulating resin is formed on an area between the two adjacent pixel electrodes 17.
In the first conventional technique above, the black matrix is formed of a metal such as chrome. However, in the second conventional technique just described above, the black matrix 18 is formed of an opaque insulating resin. Therefore, the parasitic capacitance between the black matrix made and source and drain electrodes is eliminated. In addition, the black matrix of a resin has a lower reflection coefficient than that of a metal, solving the light reflection problem.
However, when the black matrix is formed of such a resin, because of its poor light shielding capability, the black matrix must be formed as thick as 1-2 .mu.m. This results in the formation of high steps near the boundary between the black matrix and the pixel electrode. These steps cause a poor rubbing problem in that the orientation layer 19 made of polyamide or polyimide near the step can not be properly rubbed due to the steps created by the large thickness of the resin. Thus, liquid crystal placed on the poorly rubbed orientation layer is not properly oriented in a desired direction or arranged at a desired angle when a signal voltage is applied.